DSP 101
M12 · Project
Capstone project
Design one chain, stage by stage

Chain three sandboxes into one audio effects chain — design a low-pass FIR and read the latency it adds, analyse its output with an STFT and read the frequency resolution, then add a resonant IIR stage and read whether it stays stable. Predict each number before the screen shows it, and record your chain at the end.

The three stages, one signal
\begin{gathered} \tau = \tfrac{N-1}{2}\ \text{samples} \quad\text{(stage 1: latency)} \\[4pt] \Delta f = f_s / N \quad\text{(stage 2: resolution)} \\[4pt] \max_k |p_k| < 1 \quad\text{(stage 3: stable?)} \end{gathered}

A processing chain is a cascade: each stage transforms the signal and hands it to the next, so the stages interact. The FIR filter band-limits the audio but delays every sample by its constant group delay (N-1)/2 — a latency the rest of the chain inherits. The STFT that inspects the result trades window length for frequency resolution f_s/N. And a feedback (IIR) stage sharpens a resonance cheaply, but only if its poles stay inside the unit circle |z| = 1 — otherwise the whole chain blows up. This project is the interaction: lengthen the filter and the latency grows; shrink the analysis window and the resolution coarsens; push the resonator's pole outward and stability is lost.

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DSP 101
M12 · Project
Set it up
Three sandboxes, one chain

Open each of the three sandboxes in a tab. Each step below names the one sandbox to read and the single choice to make in it; leave every other knob at its default so your numbers match these. The whole chain runs at f_s = 16000 Hz.

The three stages
1 Filter designer -> Low-pass FIR, fs = 16000 Hz, cutoff = 0.10 f_s, Taps N = 101 2 Spectrogram -> fs = 16000 Hz, window N = 1024 3 Pole-zero -> Resonator preset

Read three numbers across the three tabs: the group-delay panel in the filter designer, the frequency-resolution readout in the spectrogram, and the stability verdict in the pole-zero panel.

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DSP 101
M12 · Project
Step 1 of 3
Demo · Filter designer
Filter: the latency

In the filter designer set a low-pass FIR at f_s = 16000 Hz, cutoff 0.10 f_s, with Taps N = 101. A symmetric (Type I) FIR delays every frequency by the same (N-1)/2 samples. Predict that delay, then read the group-delay panel.

Expected

The group-delay panel is a flat line at (N-1)/2 = (101-1)/2 = 50 samples — every sample the chain sees downstream arrives 50 samples late. This is the demo's own linear-phase design, not a typed number.

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DSP 101
M12 · Project
Step 2 of 3
Demo · Spectrogram
Analysis: the resolution

Feed the filtered signal into the spectrogram. Set f_s = 16000 Hz and a window of N = 1024 samples. Each DFT bin spans f_s/N hertz. Predict that resolution, then read the resolution readout.

Expected

The frequency resolution is f_s/N = 16000 / 1024 = 15.625 Hz per bin — fine enough that the filter's 1600 Hz cutoff lands cleanly around bin 102. This is the demo's own f_s/N, not a typed number.

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DSP 101
M12 · Project
Step 3 of 3
Demo · Pole-zero
Resonator: is it stable?

Add a resonant IIR boost as the last stage: load the Resonator preset in the pole-zero sandbox, keeping the conjugate-pair lock on. Feedback can blow up, so predict whether the largest pole radius max|p_k| is inside the unit circle, then read the verdict panel.

Expected

The verdict reads STABLE: the largest pole radius is max|p_k| = 0.95, strictly inside the unit circle |z| = 1, so the whole chain settles. This is the demo's own complex arithmetic, not a typed number.

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DSP 101
M12 · Project
Your turn
Assemble the chain

Open all three sandboxes and run the cascade yourself: lengthen the filter and watch the flat group-delay line climb, shrink the analysis window and watch the frequency resolution coarsen, then push the resonator's pole toward the unit circle and watch the verdict flip from stable to unstable.

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DSP 101
M12 · Project
Deliverable
Record your chain

A chain design is a set of stages and the numbers they produce. Write yours down — fill in each blank from the sandboxes, then add one sentence of reasoning. This is the deliverable; there is no number to read off the screen here.

Write this down
Stage 1 FIR filter ..... Taps N = 101, cutoff 0.10 f_s group delay ... ______ samples Stage 2 STFT analysis .. fs = 16000 Hz, N = 1024 resolution .... ______ Hz Stage 3 IIR resonator .. Resonator preset max|p_k| ...... ______ stable? Y / N Total latency .......... which stage dominates it? __________ Design note ............ which knob would you change first, and why? __________

Then change one thing — more taps, a shorter window, a pole nearer the circle — and note which of the three numbers moved and by how much. That coupling is the whole lesson of the project.

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